This invention relates to a semiconductor integrated circuit device and, particularly, to an improvement in a complementary MOS integrated circuit device (hereinafter referred to as a CMOSIC).
The CMOSIC, which exhibits low power consumption and a wide operating source voltage range, has enjoyed widespread use in the industry over the past several years. The CMOSIC of the prior art comprises a p-channel MOS transistor (p-MOST) and an n-channel MOS transistor (n-MOST) formed on a common substrate. As such, a parasitic bipolar transistor is formed between the p-type and n-type diffusion layers forming the transistors. This parasitic bipolar transistor causes the so-called "latch-up" phenomenon to occur which causes the CMOSIC element to break down. This is the most important defect of the CMOSIC devices of the prior art.
FIG. 1 is an equivalent circuit diagram of a minimum unit of the CMOS circuit, in which A is a p-MOST having a source 101 and a drain 102, and B is an n-MOST having an source 103 and a drain 104. The source 101 of the p-MOST A is connected to a voltage source terminal V.sub.DD and the source 103 of the n-MOST B is connected to a voltage source terminal V.sub.SS. The gates of the MOSTs A and B are connected to a common input terminal IN, and the drains 102 and 104 respectively are connected to a common output terminal OUT.
FIG. 2 is a cross-sectional view of a conventional CMOSIC which provides the circuit equivalent of FIG. 1 and comprises a n-type semiconductor substrate 105 including a p-type island 106 forming the n-MOST B, an insulating layer 107 formed on the substrate, metal electrodes 108, a p.sup.+ type contact layer 109 for the source terminal V.sub.SS and an n.sup.+ type contact layer 110 for the source terminal V.sub.DD.
In such a CMOSIC as described above, the parasitic bipolar transistors and resistors which contribute to the latch-up phenomenon are shown by dotted lines. One parasitic transistor 1 of pnp type is formed between the p.sup.+ type source region 101 of the p-MOST A, the p-island 106 and the n-type substrate 105. Parasitic transistor 2 of pnp type is formed between the p drain region 102 of the p-MOST A, the p-type island 106 and the n-type substrate 105. A third parasitic transistor 3 of npn type is formed between the n.sup.+ type source region 103 of the n-MOST B, the p-type island 106 and n-type substrate 105, and a fourth parasitic transistor 4 of npn type is formed between the n.sup.+ type drain regions 104 of the n-MOST B, the p-type island 106 and the n-type substrate 105. A first parasitic resistor 5 is produced from the substrate through the n.sup.+ diffusion layer 110 to the source terminal V.sub.DD, a second resistor 6 is produced within the p.sup.+ type source regions 101 of the p-MOST A, a third resistor 7 is produced from the substrate through the p-type island 109 to the source terminal V.sub.SS, and a fourth resistor 8 is produced within the n.sup.+ type source region 103 of the n-MOST B.
FIG. 3 shows the circuit diagram of these parasitic elements formed in the CMOSIC. The above-mentioned latch-up phenomenon will now be described with reference to FIGS. 2 and 3.
When a negative surge voltage is applied to the output terminal OUT, a forward current flows between the p-type island 106 and the n.sup.+ type drain 104 of the n-MOST B. With this forward current, the npn transistor 4 turns on, causing a current which is the forward current amplified by the amplification factor h.sub.FE of the npn transistor 4 to flow h.sub.FE4 from the source terminal V.sub.DD through the resistor 5 and the n-type substrate 105 to the n.sup.+ type drain 104 of the n-MOST B.
With this current, the junction between the base and emitter of the pnp transistor 1 is forward biased, causing the latter to be conductive. Therefore, a current flows from the source terminal V.sub.DD through the resistor 6, the pnp transistor 1 and the resistor 7 to the source terminal V.sub.SS. Consequently, the npn transistor 3 is forward biased, so that a portion of the base current of the pnp transistor 1 is derived out. Therefore, a large current continually flows between the source terminals V.sub.DD and V.sub.SS due to a thyristor comprising the pnp transistor 1 and npn transistor 3. Once this large current is established, it will continue to flow even if the surge input to the output terminal OUT is terminated. In this manner, the IC cannot operate in a mode other than the breakdown mode once this current is established by a negative surge at the OUT terminal.
Similarly, when a positive surge voltage is applied to the output terminal OUT, a current flows between the p.sup.+ type drain 102 of the p-MOST A and the n-type substrate 105. Therefore the pnp transistor 2 becomes conductive and a current which is a current flowing between the drain 102 of the p-MOST A and the p-island 106 amplified by the amplification factor h.sub.FE2 of the transistor 2 flows through the resistor 7 to the terminal V.sub.SS. With this current, the base-emitter circuit of the npn transistor 3 is forwardbiased and thus the latter becomes conductive causing a current to flow from the source terminal V.sub.DD through resistor 5, npn transistor 3, and resistor 8 to the source terminal V.sub.SS. With this current, the pnp transistor 1 is further forward-biased and supplies a further current to the base of the npn transistor 3. Therefore, a large current continually flows between the terinals V.sub.DD and V.sub.SS due to a thyristor formed by the pnp transistor 1 and the npn transistor 3, again resulting in the breakdown of the IC.
The formation of parasitic bipolar transistors in the CMOSIC is unavoidable. Thus, any solution to this problem must be based on the premise that the abovementioned latch-up phenonmenon is unavoidable.